(a) Field of the Invention
The present invention relates to a stacked capacitor and a method for fabricating a stacked capacitor in a semiconductor device. More specifically, the present invention relates to an improvement of characteristics of a stacked capacitor such as an anti-oxidation property and an electric resistance for the electrode thereof.
(b) Description of a Related Art
A semiconductor integrated circuit, such as a DRAM, often includes a stacked capacitor in a functional element constituting the semiconductor integrated circuit. It is desired along with the development of higher integration and finer patterning of the semiconductor device that the dimensions of the capacitor be reduced.
The technique for reduction of the dimensions of the capacitor is described in "1997 Symposium on VLSI Technology Digest of Technical Papers", pp 17 and 18, for example. In the publication, a stacked capacitor is proposed which includes a Ru film for each electrode of the stacked capacitor and a high permittivity film, such as BST film, as the capacitor insulator film.
FIGS. 1A to 1G consecutively show fabrication steps of a conventional stacked capacitor in a semiconductor integrated circuit. In fabrication of the stacked capacitor, a plurality via-holes each receiving therein a polysilicon plug 16 are formed in a first interlevel dielectric film 14, the polysilicon plug 16 being in contact with a diffused region formed in a semiconductor substrate 12. A SiN film 18 is then formed on the interlevel dielectric film 14, followed by deposition of a second interlevel dielectric film 20, whereby the structure shown in FIG. 1A is obtained. The SiN film 18 is used for improvement of adhesion between the first interlevel dielectric film 14 and the second interlevel dielectric film 20.
Subsequently, as shown in FIG. 1B, a photoresist film 24 is formed on the second interlevel dielectric film 20, followed by patterning thereof to form an etching mask 24 having openings 22 therein. The second interlevel dielectric film 20 and the SiN film 18 are then subjected to patterning using the etching mask 24 to form openings 26 each exposing the contact plug 16. Thereafter, a Ru film 28 is deposited by sputtering onto the entire area of the wafer including the inner walls of the openings 26 and on the top surface of the polysilicon plug 16 at the bottom of the opening 26.
The Ru film 28 is then subjected to a CMP process, thereby leaving a portion of the Ru film 28 as a bottom electrode on the inner wall and the bottom of the openings 26, as shown in FIG. 1E. An insulator film (BST film) 30 made of (Ba,Sr)TiO.sub.3 is then deposited on the entire area by a CVD process in an oxygen ambient. Finally, a Ru film 32 is deposited by sputtering to form a top electrode 32, to obtain the structure shown in FIG. 1G.
There are following problems in the conventional fabrication process for the stacked capacitor as described above. First, a high contact resistance appears between the polysilicon plug 16 and the bottom Ru electrode 28. This is caused mainly by oxidation of the polysilicon plug 16 due to oxygen penetrating through the bottom Ru electrode 28 during CVD of the BST film 30. The Ru film 28 has poor characteristics in stopping the penetrating oxygen due to the poor crystalline orientation alignment thereof, which in turn is caused by deposition of the Ru film 28 onto the etched surface of the openings 26. In general, a metallic film formed on the etched surface has such a poor property. The high contact resistance reduces the read/write speed of a memory cell having the stacked capacitor.
Second, the bottom Ru electrode 28 is liable to peel-off from the inner wall of the openings 26 during the CMP process of the thin Ru film 28. Although the Ru film 28 has excellent adherence to polysilicon, the adherence of the Ru film 28 to the first interlevel dielectric film 20 made of SiO.sub.2 is poor. The peel-off of the bottom Ru electrode 28 may reduce the capacitance of the resultant stacked capacitor.
Third, the impurities existing at the interface between the BST film 30 and the bottom Ru electrode 28 degrade the characteristics of the resultant capacitor. The impurities include fine particles of particle slurry or Ru film left at the interface within the openings after the CMP process for the Ru film 28. It is difficult in fact to entirely remove the remaining impurities after the CMP process. Similar situation will result if another precious metal or refractory metal is used instead of Ru.
In short, the conventional method does not provide a stacked capacitor having desired characteristics especailly for the electrodes.